The Rambus Inline Memory Encryption IP provides inline encryption, decryption, and authentication for memory read/write requests using AES and SM4 ciphers with XTS, GCM, and ECB modes. It supports multi-stream and multi-algorithm operations, enabling protection of up to 32 configurable memory regions with individual keys. Designed for high-performance applications, it offers scalable solutions for DDR and LPDDR5 memories, ensuring minimal latency and high bandwidth. The IP includes Differential Power Analysis countermeasures and datapath integrity using ECC SRAMs for robust security. It is CAVP certified and supports advanced features like ARMv9 architecture specifications, making it suitable for secure SoC designs.
